1. Field of the Invention
The present invention relates to a wafer level device package and a method of packaging the same, and more particularly, to a wafer level device package with a sealing line having an electroconductive pattern and a method of packaging the same that can seal a device and simultaneously have an electrical connection structure for the device.
2. Description of the Related Art
Recently, as semiconductor devices shrink in size, interest in wafer level package technology is rapidly growing. A wafer level package technology refers to a semiconductor package technology that packages chips at a wafer level where the chips are not cut or separated, as opposing to an existing technology that cuts a wafer into individual chips and packages them.
Specifically, a semiconductor package is fabricated through four steps: circuit design, wafer processing, assembly, and inspection. The assembly process includes a wire bonding process and a packaging process. The assembly process includes cutting a process-finished wafer into individual chips, attaching the individual chips on a small circuit board, bonding wires, and sealing the chips with a plastic package.
The wafer level packaging is accomplished by a simple procedure. That is, instead of plastic that has been used as a package material, a photosensitive insulation material is coated over the individual chips disposed on the wafer, wires are bonded, and an insulation material is again coated thereon.
Such a wafer level package technology can reduce the semiconductor assembly processes, such as the wire bonding and plastic package. Furthermore, a manufacturing cost can be remarkably reduced because the plastic, the circuit board, and the wires, which have been used for the semiconductor assembly, are not needed. In particular, since the wafer level package technology can fabricate the package with the same size as the chip, the package size can be reduced by more than about 20 percents compared with a typical chip scale package (CSP) that has been applied to the shrinkage of the semiconductor package.
As illustrated in FIG. 1, a wafer level package includes a first substrate 1 defining a device active region 4 where a lot of devices are formed. The first substrate 1 is provided for device fabrication. A second substrate 2 is attached to the first substrate 1 through support walls 3 and supported by the support walls 3. The second substrate 2 is provided for capping the device active region 4 in order to protect it. An electrode 5 for an external wire is packaged in such a state that it is arranged on the first substrate 1, without protruding over the silicon substrate 2.
Therefore, the reliability is reduced in sealing of the device active region 4. In addition, manufacturing processes become complicated and the manufacturing cost increases, because an electrode pad is needed for electrical connection.